Motivation

One of the enabling technologies for economic growth in Europe is the CMOS semiconducter technology. The advancements of CMOS technology enable new applications and services, in particular in the automotive, consumer, and communication markets. The growth of these markets is driven by new applications, which require higher bandwidth and more computational performance. This demand on the downside results in higher power consumption.

Power is thus becoming the limiting factor of further development. It requires a radical change of today's timing and area focused design flows. The required power aware design flow needs to model, analyze, and optimize the dymanic and static power consumption during all phases of the design as an integral part of the design flow rather than as an afterthought. Within a power aware design flow several techniques such as clock gating or power gating could lead to a low-power chip. These two techniques belong to a large set of dynamic power management-techniques, that enables pushing CMOS further towards higher integration and more performance.

The importance of reducing power consumption, being the main objective of the MAP2 project, is shown by the figure below. In the late 90th the heat at the surface of intel-processors was equivalent to that of hot plates. With the upcoming generation of processors, heat released by these chips per cm2 will exceed that of nuclear reactors. Without significant improvement of design tools and flows, future processor generations will even exceed an energy density of rocket nozzles.

Circuits featuring dynamic power management capabilities are now common practice; however, customization of the architecture to accommodate the power management logic and the identification of the power management conditions are tasks which are commonly executed manually by expert designers with complete knowledge of the circuit functionality, behavior, expected usage mode and domain of application.

Only few tools that help designers in generating power-managed circuits are now commercially available. Additionally, the power management capabilities that such tools can actually support are very limited in scope and applicable only to simple design scenarios.